First we will go over power distribution network issues.

High Power

• High c-load
• high fanout
• high freq
• high toggle rate

Power grid weakness

• insufficient num of layers
• in-adequate width spacing
• disconnected wire/via
• disconnected instances
• shorts
• missing via
• missing strap
• unconnected macro pins

pad related issues

• insufficient no.of pads
• uneven pad distribution
• weakly connected pads.

decap issue

• insufficient decap
• insufficient lower metal routing

simultaneous switching

• tw clustering
• clock tree clustering
• scan shift scenario

Inputs 1) LIB - tool uses lib to calculate internal power and leakager power.

2) LEF - instance without lef are not hooked up to the power grid.

3) DEF - for shorts, unconnected instances, wires, vias , missing vias.

4) SPEF - tool uses spef to compute switching/internal power.

5) STA TW - In Static check, tool uses freq, slew data and in dynamic check, TW files are used.

Grid Robustness checks

• missing vias
• unconnected instances
• shorts
• shortest path resistance

Static IR

• avg current is used
• at what corner is this calculated ?

To resolve static ir, we could try splitting the net so that fan out gets distributed.Increase strap width or add more straps. Any static IR viols is a clear significance that power grid is weak.

Increasing the clock frequency has direct impact on static IR drop, because it increases the average current drawn from the power grid.

Dynamic IR

• Dependant on the switching activity of standard cell.
• Dynamic IR drop takes into account the instantaneous current drawn from the power grid in a switching event.

To resolve dynamic IR, we can

• space the standard cells apart so that the burden on given bump to feed many std cells decreases.
• We can also downsize cells to reduce instantaneous current demand.
• splitting output cap.
• inserting decap cells
• Also, solutions used for static ir drop are applicable here too.

To understand where one should analyze IR drop in design wrt PVT/RC corners.

RC Corner: at worst RC corner.

PVT Conditions: Where we expect highest switching activity, that would be fast corner, high voltage and high temp.

It also makes sense to run IR drop analysis for worst case setup check because IR drop would most probably impact only setup timing.

For static/dynamic: It is fast process , high voltage and high temperature rc worst is the worst case. The %of vdd how it is calculated I need to understand.

EM is evaluated at typical voltage, temp, and fast corner.

Sig EM

PG EM