CMOS Designs

The physical implementation of MOS transistors (NMOS1 and PMOS2). The separation between the source and drain regions is the length of the MOS transistor.

A CMOS logic gate is built using NMOS and PMOS transistors. Below shows an example of CMOS inverter. Example 2 input CMOS NAND gate:

Modelling of CMOS cells If a cell output pin drives multiple fanout cells, the total capacitance on the output pin of the cell is the sum of all the input capacitances of the cells that it is driving plus the sum of the capacitance of all the wire segments that comprise the net plus the output capacitance of the driving cell. Note that in a CMOS cell, the inputs to the cell present a capacitive load only.