CMOS Designs

The physical implementation of MOS transistors (NMOS1 and PMOS2). The separation between the source and drain regions is the length of the MOS transistor.

A CMOS logic gate is built using NMOS and PMOS transistors. Below shows an example of CMOS inverter. Example 2 input CMOS NAND gate:

Modelling of CMOS cells If a cell output pin drives multiple fanout cells, the total capacitance on the output pin of the cell is the sum of all the input capacitances of the cells that it is driving plus the sum of the capacitance of all the wire segments that comprise the net plus the output capacitance of the driving cell. Note that in a CMOS cell, the inputs to the cell present a capacitive load only.

Discuss about transition times and slew

• A slew rate is defined as a rate of change. In static timing analysis, the rising or falling waveforms are measured in terms of whether the transition is slow or fast. The slew is typically measured in terms of the transition time, that is, the time it takes for a signal to transition between two specific levels. Note that the transition time is actually inverse of the slew rate- the larger the transition time, the slower the slew, and vice versa.

Discuss about clock uncertainity (clock skew and jitter)

• Clock latency is the total time it takes from the clock source to an end point. Clock skew is the difference in arrival times at the end points of the clock tree.
• The uncertainty in the timing of the clock edge is to account for several factors such as clock period jitter and additional margins used for timing verification. Every real clock source has a finite amount of jitter- a window within which a clock edge can occur. The clock period jitter is determined by the type of clock generator utilized. In reality, there are no ideal clocks, that is, all clocks have a finite amount of jitter and the clock period jitter should be included while specifying the clock uncertainty.
• Before clock tree is implemented, the uncertainity must also include the clock skew that is expected.
• One can specify different clock uncertainties for setup checks and for hold checks. The hold checks do not require the clock jitter to be included in the uncertainty and thus a smaller value of clock uncertainty is generally specified for hold.

Discuss about PVT operating conditions Process: s (worst case speed, best case leakage) f (best case speed, worst case power) t () PVT for cell: worst case slow: process (s), voltage (low), temp (high) , at nm due to temp inversion, temp (low) is also considered worst case slow. best case fast: process (f), voltage (high), temp (low) Conditions for power analysis: maximum leakage: process (f) , voltage (high), temp (high) typical leakage: process (t), voltage (nominal), temp (high).