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Standard cell Library
This chapter describes about timing information present in the standard cell library. I could be NOR or a IP or any cell. In addition to timing information, the library cell description contains several attributes such as cell area and functionality, which are unrelated to timing but are relevant during the RTL synthesis process. In this chapter, we focus only on the attributes relevant to the timing and power calculations.
The initial sections in this chapter describe the linear and the non-linear timing models followed by advanced timing models for nanometer technologies
1. Pin Capacitance:
Every input and output of a cell can specify capacitance at the pin. In most cases, the capacitance is specified only for the cell inputs and not for the outputs, that is, the output pin capacitance in most cell libraries is 0.
2. Timing Models:
The cell timing models are intended to provide accurate timing for various instances of the cell in the design environment. The timing models are nomally obtained from detailed circuit simulations of the cell to model the actual scenario of the cell operation. The timing models are specified for each timing arc of the cell. The delay for the timing arc through the inverter cell is dependent on two factors: i.the output load, that is, the capacitance load at the output pin of the inverter, and ii. the transition time of the signal at the input The delay values have a direct correlation with the load capacitance- the larger the load capacitance, the larger the delay. In most cases, the delay increases with increasing input transition time. There are a few scenarios where the input threshold (used for measuring delay) is significantly different from the internal switching point of the cell. In such cases, the delay through the cell may show non-monotonic behavior with respect to the in put transition time- a larger input transition time may produce a smaller delay especially if the output is lightly loaded.
The slew at the output of a cell depends mainly upon the output capacitance- output transition time increases with output load. Thus, a large slew at the input (large transition time) can improve at the output depending upon the cell type and its output load. Figure shows cases where the transition time at the output of a cell can improve or deteriorate depending on the load at the output of the cell.