Interconnect Parasitics

After physical implementation, the net can travel on multiple metal layers of the chip. Various metal layers can have different resistance and capacitance values. For equivalent electrical representation, a net is typically broken up into segments with each segment represented by equivalent parasitics. We refer to an intercon nect trace as a synonym to a segment, that is, it is part of a net on a specific metal layer.

4.1 RLC for Interconnect

The interconnect resistance comes from the interconnect traces in various metal layers and vias in the design implementation. Figure 4-1 shows ex ample nets traversing various metal layers and vias. Thus, the interconnect resistance can be considered as resistance between the output pin of a cell and the input pins of the fanout cells.

The interconnect capacitance contribution is also from the metal traces and is comprised of grounded capacitance as well as capacitance between neighboring signal routes. The inductance arises due to current loops. Typically the effect of inductance can be ignored within the chip and is only considered for package and board level analysis. . In chip level designs, the current loops are narrow and short- which means that the current return path is through a power or ground signal routed in close proximity. In most cases, the on-chip inductance is not considered for the timing analysis.

The resistance and capacitance (RC) for a section of interconnect trace is ideally represented by a distributed RC tree as shown in Figure 4-2. In this figure, the total resistance and capacitance of the RC tree- Rt and Ct respectively- correspond to Rp* L and Cp* L where Rp, Cp are per unit length val ues of interconnect resistance and capacitance for the trace and L is the trace length. The Rp, Cp values are typically obtained from the extracted parasitics for various configurations and is provided by the ASIC foundry.

The RC interconnect can be represented by various simplified models.

T - Model In the T-model representation, the total capacitance Ct is modeled as connected halfway in the resistive tree. The total resistance Rt is broken in two sections (each being Rt / 2), with the Ct connection represented at the mid point of the resistive tree as shown in Figure 4-3.

Pi-Model In the Pi-model shown in Figure 4-4, the total capacitance Ct is broken into two sections (each being Ct / 2) and connected on either side of the resis tance.

4.2 Wireload Models

Prior to floorplanning or layout, wireload models can be used to estimate capacitance, resistance and the area overhead due to interconnect. The wireload model is used to estimate the length of a net based upon the number of its fanouts. The wireload model also maps the estimated length of the net into the re sistance, capacitance and the corresponding area overhead due to routing.

The average wire length within a block correlates well with the size of the block; average net length increases as the block size is increased. Figure 4-7 shows that for different areas (chip or block size), different wireload models would typically be used in determining the parasitics. Thus, the figure depicts a smaller capacitance for the smaller sized block. The slope is the extrapolation slope to be used for data points that are not specified in the fanout length table.

4.2.1 Interconnect Trees

Once the resistance and capacitance estimates, say Rwire and Cwire, of the pre-layout interconnect are determined, the next question is on the struc ture of the interconnect. How is the interconnect RC structure located with respect to the driving cell? This is important since the interconnect delay from adriver pin to a load pindependsuponhowtheinterconnectis structured. In general, the interconnect delay depends upon the interconnect re sistance and capacitance along the path. Thus, this delay can be different depending on the topology assumed for the net. For pre-layout estimation, the interconnect RC tree can be represented using one of the following three different representations (see Figure 4-9). Note that the total interconnect length (and thus the resistance and capacitance estimates) is the same in each of the three cases. • Best-case tree: In the best-case tree, it is assumed that the destination (load) pin is physically adjacent to the driver. Thus, none of the wire resistance is in the path to the destination pin. All of the wire capaci tance and the pin capacitances from other fanout pins still act as load on the driver pin. • Balanced tree: In this scenario, it is assumed that each destination pin is on a separate portion of the interconnect wire. Each path to the destination sees an equal portion of the total wire resistance and ca pacitance. • Worst-case tree: In this scenario, it is assumed that all the destination pins are to gether at the far end of the wire. Thus each destination pin sees the total wire resistance and the total wire capacitance.

4.2.1 Specifying Wireload Models

Wireload models are typically defined in a cell library- however a user can define a custom wireload model as well. A default wireload model may optionally be specified in the cell library. This section described the modeling of estimated parasitics before the physical implementation, that is, during the pre-layout phase. The next section describes the representation of parasitics extracted from the layout.

4.3 Representation of extracted parasitics

Parasitics extracted from a layout can be described in three formats: i. Detailed Standard Parasitic Format (DSPF): Pro, written in SPICE , can also be used in SPICE simulations. COn: very large, can only be used for small or selected nets. ii. Reduced Standard Parasitic Format (RSPF): . The RSPF format requires that the detailed parasitics are reduced and mapped into the reduced format. This is thus a drawback of the RSPF representation since the focus of the parasitic extraction process is normally on the extraction accuracy and not on the reduction to a compact format like RSPF. One other limitation of the RSPF representation is that the bidirectional signal flow cannot be represented in this format. iii. Standard Parasitic Extraction Format (SPEF): TheSPEFisacompact formatwhichallowstherepresentationofthede tailedparasitics.

4.4 Representing Coupling Capacitances

4.5 Hierarchical Designs

The layout extracted parasitics of a block may be utilized for timing verification with another block whose layout has not been completed. In this scenario, layout extracted parasitics of layout-complete blocks are often used with wireload model based parasitic estimates for the pre-layout blocks. In the case of the hierarchical flow, where the top level layout is complete but the blocks are still represented as black boxes (pre-layout), wireload model based parasitic estimates can be used for the lower level blocks along with the layout extracted parasitics for the top level. Once the layout of the blocks is complete, layout extracted parasitics for the top and the blocks can be stitched together Block Replicated in Layout If a design block is replicated multiple times in layout, the parasitic extraction for one instantiation can be utilized for all instantiations. This requires that the layout of the block be identical in all respects for various instantiations of the block. For example, there should be no difference in terms of layout environment as seen from the nets routed within the block. This implies that the block level nets are not capacitively coupled with any nets outside the block. One way this can be achieved is by ensuring that no top level nets are routed over the blocks and there is adequate shielding or spacing for the nets routed near the boundary of the block.

4.6 Reducing Parasitics for Critical Nets

DEEP DIVE INTO THIS AREA FURTHER

Reducing Interconnect Resistance Widetrace: Having a trace wider than the minimum width reduces interconnect resistance without causing a significant increase in the parasitic capacitance. Thus, the overall RC interconnect delay and the transition times are reduced. Routing in upper (thicker) metals: The upper metal layer(s) normally have low resistivity which can be utilized for routing the critical signals. The low interconnect resistance reduces the interconnect delay as well as the transition times at the destination pins.

Increasing Wire Spacing Increasing the spacing between traces reduces the amount of coupling (and total) capacitance of the net. Large coupling capacitance increases the crosstalk whose avoidance is an important consideration for nets routed in adjacent traces over a long distance.

Parasitics for Correlated Nets In many cases, a group of nets have to be matched in terms of timing. An example is the data signals within a byte lane of a high speed DDR inter face. Since it is important that all signals within a byte lane see identical parasitics, the signals are all routed in the same metal layer. For example, while metal layers M2 and M3havethesame average andthe samestatistical variations, the variations are independent so that the parasitic varia tions in these two metal layers do not track each other. Thus, if it is important for timing to match for critical signals, the routing must be identical in each metal layer.