Delay Calculation

5.1 Delay Calculation with interconnect in prelayout timing As described in Chapter 4, the interconnect parasitics are estimated using wireload models during the pre-layout timing verification. In many cases, the resistance contribution in the wireload models is set to 0. In such scenarios, the wireload contribution is purely capacitive and the delay calcu lation methodology described in the previous section is applicable to obtain the delays for all the timing arcs in the design. In cases where the wireload models include the effect of the resistance of the interconnect, the NLDM models are used with the total net capacitance for the delay through the cell. Since the interconnect is resistive, there is additional delay from the output of the driving cell to the input pin of the fanout cell.

5.2 Delay Calculation with interconnect in postlayout timing##

Cell delay using effective capacitance: As described above, the NLDM models are not directly usable when the load at the output of the cell includes the interconnect resistance. Instead, an “effective” capacitance approach is employed to handle the effect of re sistance. The effective capacitance approach attempts to find a single capacitance that can be utilized as the equivalent load so that the original design as well the design with equivalent capacitance load behave similarly in terms of timing at the output of the cell. This equivalent single capacitance is termed as effective capacitance.

The effective capacitance is a function of: i.the driving cell, and ii. the characteristics of the load or specifically the input impedance of the load as seen from the driving cell.

The effective capacitance approximation is thus a good model for computing delay through the cell. However, the output slew obtained using effec tive capacitance does not correspond to the actual waveform at the cell output. The waveform at the cell output, especially for the trailing half of the waveform, is not represented by the effective capacitance approximation. Note that in a typical scenario, the waveform of interest is not at the cell output but at the destination points of the interconnect which are the input pins of the fanout cells.

There are various approaches to compute the delay and the waveform at the destination points of the interconnect. In many implementations, the effective capacitance procedure also computes an equivalent Thevenin voltage source for the driving cell. The Thevenin source comprises of a ramp source with a series resistance Rd as shown in Figure 5-6. The series resistance Rd corresponds to the pull-down (or pull-up) resistance of the output stage of the cell.

Interconnect Delay

Higher Order Interconnect Delay Estimation As described above, the Elmore delay is the first moment of the impulse response. The AWE (Asymptotic Waveform Evaluation), Arnoldi or other methods match higher order moments of response. By considering the higher order estimates, greater accuracy for computing the interconnect delays is obtained.

Full Chip delay calculation. So far, this chapter has described the computation of delays for a cell and the interconnect at the output of a cell. Thus, given the transition at the in puts of the cell, the delays through the cell and the interconnect at the out put of the cell can be computed. The transition time at the far-end of the interconnect (destination or sink point) is the input to the next stage and this process is repeated throughout the entire design. The delays for each timing arc in the design are thus calculated.

5.3 Slow Merging

What happens when multiple slews arrive at a common point, such as in the case of a multi-input cell or a multi-driven net? Such a common point is referred to as a slew merge point. Which slew is chosen to propagate for ward at the slew merge point? Consider the 2-input cell shown in Figure 5-10

The slew at pin Z due to signal changing on pin A arrives early but is slow to rise (slow slew). The slew at pin Z due to signal changing on pin B arrives late but is fast to rise (fast slew). At the slew merge point, such as pin Z, which slew should be selected for further propagation? Either of these slew values may be correct depending upon the type of timing analysis (max or min) being performed as described below.

There are two possibilities when doing max path analysis: i.Worst slew propagation: This mode selects the worst slew at the merge point to propagate. This would be the slew in Figure 5 10(a). For a timing path that goes through pins A->Z, this selec tion is exact, but is pessimistic for any timing path that goes through pins B->Z. ii. Worst arrival propagation: This mode selects the worst arrival time at the merge point to propagate. This corresponds to the slew in Figure 5-10(b). The slew chosen in this case is exact for a timing path that goes through pins B->Z but is optimistic for a timing path that goes through pins A->Z.

Similarly, there are two possibilities when doing min path analysis: i.Best slew propagation: This mode selects the best slew at the merge point to propagate. This would be the slew in Figure 5 10(b). For a timing path that goes through pins B->Z, this selec tion is exact, but the selection is smaller for any timing path that goes through pins A->Z. For the paths going through A->Z, the path delays are smaller than the actual values and is thus pessi mistic for min path analysis. ii. Best arrival propagation: This mode selects the best arrival time at the merge point to propagate. This corresponds to the slew in Figure 5-10(a). The slew chosen in this case is exact for a timing path that goes through pins A->Z but the selection is larger than the actual values for a timing path that goes through pins B->Z. For the paths going through B->Z, the path delays are larger than the actual values and is thus optimistic for min path analy sis.

Adesigner may perform delay calculation outside of the static timing anal ysis environment for generating an SDF. In such cases, the delay calcula tion tools normally use the worst slew propagation. The resulting SDF is adequate for max path analysis but may be optimistic for min path analy sis. Most static timing analysis tools use worst and best slew propagation as their default as it bounds the analysis by being conservative. However, it is possible to use the exact slew propagation when a specific path is being an alyzed. The exact slew propagation may require enabling an option in the timing analysis tool. Thus, it is important to understand what slew propa gation mode is being used by default in a static timing analysis tool, and understand situations when it may be overly pessimistic.

5.4 Different Slew Thresholds

In general, a library specifies the slew (transition time) threshold values used during characterization of the cells. The question is, what happens when acell with one set of slew thresholds drives other cells with different set of slew threshold settings? Consider the case shown in Figure 5-11 where a cell characterized with 20-80 slew threshold drives two fanout cells; one with a 10-90 slew threshold and the other with a 30-70 slew threshold and a slew derate of 0.5.

5.4 Different Voltage domains

A typical design may use different power supply levels for different por tions of the chip. In such cases, level shifting cells are used at the interface between different power supply domains. A level shifting cell accepts in put at one supply domain andprovides output at theother supply domain. As an example, a standard cell input can be at 1.2V and its output can be at a reduced power supply, which may be 0.9V. Figure 5-12 shows an exam ple. Notice that the delay is calculated from the 50% threshold points. These points are at different voltages for different pins of the interface cells.

5.5 Combinational Path Delay