Timing Verification

The two primary checks are the setup and hold checks. Once a clock is de fined at the clock pin of a flip-flop, setup and hold checks are automatically inferred for the flip-flop. Setup Timing Check The data should be stable for a certain amount of time, namely the setup time of the flip-flop, before the active edge of the clock arrives at the flip-flop. This requirement ensures that the data is captured reliably into the flip-flop The setup check can be mathematically expressed as: Tlaunch + Tck2q + Tdp < Tcapture + Tcycle- Tsetup

Tlaunch: delay of clock tree to launch flop.

As described in previous chapters,thecelldelayiscalculatedbasedontheinputtransi tiontimeandtheoutputcapacitanceofthecell.Thus,thequestioniswhat transitiontimeisusedat theinputof thefirstcell intheclocktree.The transitiontime(orslew)ontheinputpinofthefirstclockcellcanbeexplic itlyspecifiedusingtheset_input_transitioncommand.

What is clock source latency? This is also called insertion delay and is the time it takes for a clock to propagate from its source to the clock definition point of the design under analysis as depicted in Figure 8-3. This corresponds to the latency of the clock tree that is outside of the design. For example, if this design were part of a larger block, the clock source latency specifies the delay of the clock tree up to the clock pin of the design under analysis. Mainly we can see clock source latency in PT when HScontext is consumed.

Hold Timing Check The hold specification of a flip-flop requires that the data being latched should be held stable for a specified amount of time after the active edge of the clock.

a hold timing check is between the launch flip flop- the flip-flop that launches the data, and the capture flip-flop- the flip-flop that captures the data and whose hold time must be satisfied.

The hold time check verifies that the difference be tween these two times (data arrival time and clock arrival time at capture flip-flop) must be larger than the hold time of the capture flip-flop, so that the previous data on the flip-flop is not overwritten and the data is reliably captured in the flip-flop.

Tlaunch + Tck2q + Tdp > Tcapture + Thold

While setup violations can cause the operating frequency of the design to be lowered, the hold violations can kill a design, that is, make the design inoperable at any frequency. Thus it is very important to understand the hold timing checks and resolve any violations.

MultiCycle Paths

The default hold check edge is always: “one active edge prior to the setup capture edge”

Crossing Clock Domains

False Paths

Half Cycle Paths If a design has both negative-edge triggered flip-flops (active clock edge is falling edge) and positive-edge triggered flip-flops (active clock edge is ris ing edge), it is likely that half-cycle paths exist in the design. A half-cycle path could be from a rising edge flip-flop to a falling edge flip-flop, or vice versa. Figure 8-19 shows an example whenthelaunch is on the falling edge of the clock of flip-flop UFF5, and the capture is on the rising edge of the clock of flip-flop UFF3.

Removal Timing Check A removal timing check ensures that there is adequate time between an active clock edge and the release of an asynchronous control signal. The check ensures that the active clock edge has no effect because the asynchro nous control signal remains active until removal time after the active clock edge. In other words, the asynchronous control signal is released (becomes inactive) well after the active clock edge so that the clock edge can have no effect. (like a hold check).

Recovery Timing Check A recovery timing check ensures that there is a minimum amount of time between the asynchronous signal becoming inactive and the next active clock edge. In other words, this check ensures that after the asynchronous signal becomes inactive, there is adequate time to recover so that the next active clock edge can be effective. (like a setup check)

Timing Across Cross domains Slow to Fast clock domain When the clock frequencies are different for the launch flip-flop and the capture flip-flop, STA is performed by first determining a common base period. An example of a message produced when STA is performed on such a design with the above two clocks is given below. The faster clock is expanded so that a common period is obtained.

The-end is the default for a multicycle setup and the-start is the default for multicycle hold. For slow to fast, the MCP are written wrt end clock for setup/hold.

Fast to Slow clock domain Default checks: Similartothesetupchecks,therearefourholdcheckspossible.Figure8-26 showsthemostrestrictiveholdcheckwhichensuresthatthecaptureedge at0nsdoesnotcapturethedatabeinglaunchedat0ns.

In general, a designer may specify the data path from the fast clock to the slow clock to be a multicycle path. If the setup check is relaxed to provide two cycles of the faster clock for the data path, the following is included for this multicycle specification: set_multicycle_path 2-setup -from [get_clocks CLKP]-to [get_clocks CLKM]-start set_multicycle_path 1-hold -from [get_clocks CLKP]-to [get_clocks CLKM]-start

The-start option refers to the launch clock and is

the default for a multicycle hold.

nlike the case of paths from slow to fast clock domains, a good rule of thumb for multi-frequency multicycle path specification in the case of paths from fast to slow clock domains is to use the-start option. The setup and hold checks are then adjusted based upon the fast clock.

Examples Example 1: Half cycle path from CLKM to CLKP Case2: similar as above shifted in time Case3: Fast to slow