Interface Analysis and Robust Verification

Section1: IO Interfaces

<Question why we need generated clocks and esp why div by 1 generated clock> **On-Chip Variation** **Time Borrowing** **Data to Data Checks** <READ ABOUT CAN WE GIVE MCP HOLD -1 , IF YES, HOW DOES IT BEHAVE> **ClockGating Checks** **Power Management** In this section, we focus on the tradeoffs for power dissipated in the logic portion of the design. As described in Chapter 3, the power dissipated in the logic portion of the design is comprised of leakage power and the active power. In general, there are two considerations for managing the power contribu tions from the digital logic comprised of standard cells and memory mac ros: • To minimize the total active power of the design. A designer would ensure that the total power dissipation stays within the available power limit. There may be different limits for different operating modes of the design. In addition, there can also be different lim its from different power supplies used in the design. • To minimize the power dissipation of the design in standby mode. This is an important consideration for battery operated devices (for example, cell phone) where the goal is to minimize the power dissipation in standby mode. The power dissipation in standby mode is leakage power plus any power dissipation for the logic that is active in standby mode. As discussed above, there may be other modes such as sleep mode, with different constraints on power **Active power: 1. Clock Gating**: As described in Chapter 3, clock activity at the flip-flops contributes to a significant component of the total power. A flip-flop dissipates power due to clock toggle even when the flip-flop output does not switch. **2.Active power: Power Gating**: **Leakage Power: 3. Multi Vt cells**: the multi Vt cells are used to trade off speed with leakage. The high Vt cells have less leakage, though these are slower than the standard Vt cells which are faster but have higher leak age. Similarly, the low Vt cells are faster than standard Vt cells but the leak age is also correspondingly higher. In most designs, the goal is to minimize the total power while achieving the desired operational speed. Even though leakage can be a significant component of the total power, implementing a design with only high Vt cells to reduce leakage can increase the total power even though the leak age contribution may be reduced. This is because the resulting design im plementation may require many more (or higher strength) high Vt cells to achieve the required performance. **The increase in equivalent gate count can increase the active power much more than the reduction in leakage power due to use of high Vt cells. However, there are scenarios where the leakage is a dominant component of the total power; in such cases, a de sign with high Vt cells can result in reduction of the total power**. The above trade-off between cells with different Vt in terms of their speed and leak age needs to be utilized suitably since it is dependent on the design and its switching activity profile. Two scenarios of a high performance block are illustrated below where the implementation approach can be different de pending on whether the block is very active or has low switching activity. **High Performance Block with High Activity** This scenario is of a high performance block with high switching activity and the power is dominated by the active power. For such blocks, focus sing only on reducing leakage power can cause the total power to increase even though the leakage contribution may be minimized. In such cases, the initial design implementation should use standard Vt (or low Vt) cells to meet the desired performance. After the required timing is achieved, the cells along the paths which have positive timing slack can be changed into high Vt cells so that the leakage contribution is reduced while still meeting the timing requirement. Thus, in the final implementation, the standard Vt (or low Vt) cells are used only along the critical or hard to achieve timing paths, whereas cells along the non-critical timing paths can be high Vt cells. **High Performance Block with Low Activity** This scenario is of a high performance block with very low switching activ ity so that the leakage power is a significant component of the total power. Since the block has low activity, the active power is not a major component for the total power of the design. For such blocks, the initial implementa tion attempts to use only high Vt cells in the combinational logic and flip flops. An exception is the clock tree which is always active and therefore is built with standard Vt (or low Vt) cells. After the initial implementation with only high Vt cells, there may be some timing paths where the re quired timing cannot be achieved. The cells along such paths are then re placed with standard Vt (or low Vt) cells to achieve the required timing performance. **Well Bias**: **SignOff Methodology**: STA can be run for many different scenarios. The three main variables that determine a scenario are: • Parasitics corners (RC interconnect corners and operating condi tions used for parasitic extraction) • Operating mode • PVTcorner Based upon the interconnect R and C for various corners described above, an interconnect corner with larger C results in smaller R and a corner with smaller C results in larger R. Thus, the R partially compensates for the C across various interconnect corners. This implies that no single corner maps to an extreme value (worst-case or best-case) for path delay for all types of nets. The path delay using Cworst / Cbest corners is extreme only for short nets while RCworst / RCbest corners is extreme only for long nets. **Statstical Static Timing Analysis** In practice, the WCS or BCF for the process and operating corner condi tions typically used during the STA correspond to the extreme 3s corners2. The timing libraries are based upon the process corner models provided by the foundry and characterized with the operating conditions which result in the corresponding corner for the timing values of the cells. For example, the best-case fast library is characterized using fast process models, highest power supply and lowest temperature. The sigma here refers to standard deviation of an independent variable modeled statistically. **Process and Interconnect Variations** The local process variations are one of the variations intended to be cap tured in the analysis using OCV modeling, described in Section 10.1. Since statistical timing models normally include the local process variations, the OCV analysis using statistical timing models should not include the local process variation in the OCV setting **Common fixes** Large Delays and Transition Times Onekey item is to check for unusually large values for the delays or transi tion times along the data path. Some of these can be due to: • High-fanout nets: Nets which are not buffered properly. • Longnets: Nets which need buffer insertion in between. • Low strength cells: Cells which may not have been replaced be cause these are labeled as don’t touch in the design. • Memorypaths:Paths thattypically fail due to large setup times on memoryinputs and large output delays on memory outputs Path Still Not Meeting Timing If the data path appears to have good strong cells and if the path is still fail ing timing, one needs to examine the pins where the routing delay and wireload is high. This can be the next source of improvement. Maybe the cells can be moved closer andconsequently the wireload andthe wire rout ing delay can be decreased What if Timing Still Cannot be Met Onecan utilize useful skew to help close the timing. Useful skew is where one purposely imbalances the clock trees, especially the launch and cap ture clock paths of a failing path so that the timing passes on that path. It typically means that the capture clock can be delayed so that the clock at the capture flip-flop arrives later when the data is ready. This does assume that there is enough slack on the succeeding data paths, that is, the data path for the next stage of flip-flop to flip-flop paths. The reverse can also be attempted, that is, the launch clock path can be made shorter so that the data from the launch flip-flop is launched earlier to help meet the setup timing. Once again this can only be done if the pre ceding stage of flip-flop to flip-flop paths have the extra slack to give away. Useful skew techniques can be used to fix both setup and hold violations. Onedisadvantage of this technique is that if the design has multiple modes of operation, then useful skew can potentially cause a problem in another mode. Checking Clock Domain Crossing Tools are available to ensure that all clock domain crossings in a design are valid. These tools may also have the capability to automatically generate the necessary false path specifications. Such tools may also be able to iden tify illegal clock domain crossing, that is, cases where data is crossing two different clock domains without any clock synchronization logic. In such cases, the tools may provide the capability to automatically insert suitable clock synchronization logic where required. Note that not all asynchro nous clock domain crossings require clock synchronizers. The requirement depends upon the nature of the data and whether it needs to be captured on the next cycle or a few cycles later. An alternate way of checking asynchronous clock crossings using STA is to set a large clock uncertainty that is equal to the period of the sampling clock. This ensures that there will at least be some violations based upon which one can determine the appropriate path exceptions, or add the clock synchronization logic to the design.