Here we discuss about various types of design rule checks (DRC) violation, their causes and how to fix the various design rule checks (DRC) at lower technology node on block level as well as full chip level implementation while meeting the design rule with respect to latest technology standards.

Design rule checks are nothing but physical checks of metal width, pitch and spacing requirement for the different layers which depend on different technology nodes. We need to clean up the DRC of the design because there is a logical connection of various components, and if they are physically connected, then it will fail the functionality of the chips, and chips won’t be able to perform a specific task.

The layout of a design must be in accordance with a set of predefined technology rules given by the foundry for manufacturability. After completion of the layout and its physical connection, an automatic program will check each and every polygon in the design against these design rules and report any violations. This whole process is called Design Rule Checking (DRC). There are many design rules at different technology nodes, a few of which are mentioned below.

Types of DRCs:

• Minimum width and spacing for metal
• Minimum width and spacing for via
• Fat wire Via keep out Enclosure
• End of Line spacing
• Minimum area
• Over Max stack level
• Wide metal jog
• Misaligned Via wire
• Different net spacing
• Special notch spacing
• Shorts violation
• Different net Via cut spacing
• Less than min edge length