This post is dedicated for Hold 1) Do we check hold timing in PLACE stage? Yes, ideally it should be clean. But there could be cases where we might have to recheck from post cts when a child NDM is from post cts, te results in PLACE wont be accurate. But yes, checking for hold in PLACE reports any systemic issues in the design that we can share early to RTL team.

2) Do we fix hold during cts/post cts or PRO ? We do hold fixing both at clock opt and PRO.

Congestion 1) we see congestion from cts/route but not in place. why? a) could be that the density settings used between place and post place are different. b) addition of new clock cells, hold buffers might be the new congestion hot spot. c) if there are layer constraint settings that exist in post place but not in place.