MISC TOPICS

Section 1: Pros and Cons of switchable and aon voltage area

Section 2: Power Switch Structure: type of cell and size; Interms of rush current and turn on time Section 3: What things are factored into power grid design, input factors for power grid style? Section 4: Relation between leakage power and size of the cell Section 5: abutt vs non abutt floorplan pros and cons Section 6: Gate Level Power Optimization Techniques

1. using complex cells: If a net has a much higher activity than its fan-in or fan-out nets, collapsing the high activity net into one complex cell can reduce the overall dynamic power. This is because collapsing reduces the capacitance for the high activity net.
2. cell sizing: Downsizing the cells on the non-critical paths can help reduce the dynamic power consumption.
3. appropriate slew target for the design: In general, having a very slow transition time (or slew) can lead to higher dynamic power. However, targeting very fast slew can lead to too many repeater stages which can cause congestion and can contribute to higher leakage power. Thus, the slew rate values targeted during an implementation depends upon the frequency of operation.
4. pin swapping: In certain cells, pins with equivalent functionality can have different input capaci tances. In such cases, it is bene fi cial to move the high activity net to the pin with the lower capacitance.
5. boolean factoring: Boolean factoring can be applied on a net with high activity to factor out the high activity net. This minimizes the number of logic fanouts for the high activity net.
6. back bias for leakage: Back bias is the technique of dynamically changing the threshold voltage (Vt) of a CMOS transistor. Increasing the threshold voltage of a transistor reduces its leak age current, but performance gets degraded.
7. switching off power for inactive blocks:
8. decoupling capacitances: for dynamic ir drop. con: leakage