1. Check_timing

1. TCK -001: reported endpoint is unconstrained
2. TCK -002: register clock pin have no fanin clocks.
3. TCK -012: input port has no relate clock delay set.
4. TCK -013: clocks at the gated clock point has no fanout.

2. We have a shift register with 4 back to back Flip Flops. Each flop has +ve clock-to-q delay and +ve hold time requirement. Is it possible for this path to have hold violations?

Yes — in fact, back-to-back flop paths (zero or near-zero combinational logic) are the most susceptible paths to hold violations in real silicon. Here’s why.

The hold check equation

For a launch flop (FF_i) driving a capture flop (FF_i+1) directly:

Tcq_min(launch) + Tcombo_min >= Thold(capture) + Tskew

3. How would you constrain an asynchronous FIFO?

Set set_false_path (or max_delay) specifically between the outputs of the source register and the input of the first synchronizer flop only (not chained further) — this confines the exception to exactly the metastability-prone crossing. Ensure the synchronizer flops are physically placed close together during placement (some flows use set_max_delay tightly, e.g. 1 cycle of the faster clock, rather than a pure false path, to bound routing delay and keep MTBF reasonable) — a fully unconstrained false path can let P&R route the sync chain arbitrarily far apart, hurting MTBF.

4. Is it better to have a high threshold voltage or a low threshold voltage, and why?

5. Floorplanning options

6. Why wire delay dominates gate delay in 7nm and 5nm designs?