If no multi-cycle is defined, then default setup check happens after one clock cycle and hold check happens at same clock edge as launch. This looks something like below:

Incase, combinational datapath delay is such that it takes 3 clock cycles to propagate the data from launch to capture flop then there should be MCP defined for setup check:

set_multicycle_path 3 -setup -from [get_pins <launch_flop/Q] -to [get_pins <capture_flop/D]

The important note is that if we have not defined the corresponding hold MCP, then default hold check applies (i.e hold check will happen one cycle prior to setup check with MCP).

Below figure gives more details if observed carefully. The setup check is done at clock edge 3, while default hold check will be done at clock edge 2 (i.e clock edge prior to setup clock edge with MCP).

There is a problem with such MCP constraint (where only setup MCP is given but not hold MCP). The intended hold check should be done at the same launch edge i.e o (launch) to o (capture). So, the corresponding hold constraint should be:

set_multicycle_path 2 -hold -from [get_pins /Q] -to [get_pins /D]

So, in general in most of the designs, a MCP of setup of ‘N’ clock cycles should be provided with corresponding hold MCP of ‘(N-1)’ clock cycles.

update on 01.03.2021 from another article

Here we will discuss about multicycle paths in single clock domain and in crossclock domains. So, In total we will discuss 3 cases.

1) Multicycle path for single clock domain.

2) Multicycle path for slow clock domain to Fast clock domain.

• when giving x multicycle for setup (wrt -end) we need to give x-1 cycle for hold (wrt -end). -end means capture edge shift. -start means launch edge shift.

3) Multicycle path for fast clock domain to slow clock domain.

• when giving x multicycle for setup (wrt -start) we need to give x-1 cycle for hold (wrt -start).