Net delay is the diff btw the time a signal is first applied to the net and the time it reaches other devices connected to that net.

It is due to the finite resistance and capacitance of the net.

Wire delay = func of (Rnet, Cnet + Cpin) Net delay is calculated using Rs and Cs. There are several factors which affect net parasitic:

• Net length.
• Net cross sectional area.
• Resistivity of material used.
• Proximity to other nets (crosstalk)

Post-layout design is annotated with RCs extracted from layout for better accuracy. Annotated RCs override information from WLM.

When the wires are short, the cross section of the wire is large or the interconnect material used has a low resistivity, a capacitive only model can be used.

C = eA/thickness ; A = LW

R = pL/A ; A = W*H H is height(thickness)

Higher metal layers have higher thickness (that is height), means higher cap. Hence use it for global signals.

##Elmore delay Model

Delay at node 1: Tow d1 = R1C1

Delay at node 2: Tow d2= (R1+R2)C2

Delay at node 3: Tow d3 = (R1+R2+R3)C3

τdi=R1C1+(R1+R2)C2+……..+(R1+R2+R3+…..+Ri)Ci

If, R1=R2=R3=….=R

C1=C2=C3=…..C then

τdi=RC+2RC+……..+nRC

τd=L/N.R.L/N.C+ 2 (L/n.r+L/N.C)+……

=(L/N)2(RC+2RC+…….+NRC)

=(L/N)2. N(N+1)

or τd=RC.L2/2

The delay of a wire is a quadratic function of its length

=> doubling the length of the wire quadruples its delay