The cell timing models are intended to provide accurate timing for various instances of the cell in the design environment. The timing models are normally obtained from detailed circuit simulations of the cell to model the actual scenario of the cell operation. The timing models are specified for each timing arc of the cell.

Notice that the delays are measured based upon the threshold points defined in a cell library which is typically 50% Vdd. Thus, delays are measured from input crossing its threshold point to the output crossing its threshold point.

The delay for timing arc thr inverter cell is dependent on 2 factors:

• output load cap that is pin cap plus net cap.
• input transition time.

The slew at the output of a cell depends mainly upon the output capacitance - output transition time increases with output load.

Linear Timing Model In this the delay and the output transition time of cells are represented as linear functions of the two-parameter: input transition time and output load capacitance.

The general form of a linear delay model is D = D0 + D1 * S + D2 * C

Where D0, D1, D2 are constant, S is the input transition time, and C is the output load capacitance.

The linear delay models are not accurate over the range of input transition time and output capacitance for deep submicron technologies so presently most of the cell libraries use the more complex models like Non-linear Delay Model (NLDM) and CCS model.

Non-Linear Delay Model Most of the cell libraries include table models to specify the delays and timing checks for various timing arcs of the cell. Some newer timing libraries for nanometer technologies also provide current source based advanced timing models (such as CCS, ECSM, etc.)

The table models are referred to as NLDM (Non-Linear Delay Model) and are used for delay, output slew, or other timing checks. The table models capture the delay through the cell for various combinations of input transition time at the cell input pin and total output capacitance at the cell output.

An NLDM model for delay is presented in a two-dimensional form, with the two independent variables being the input transition time and the output load capacitance, and the entries in the table denoting the delay.

We will have 4 such tables for cell rise, cell fall, rise_transition and fall_transition.

If the table does not have an entry then interpolation is done.

slew derating The slew1 values are based upon the measurement thresholds specified in the library.
Most of the previous generation libraries (0.25mm or older) used 10% and 90% as measurement thresholds for slew or transition time.

As technology becomes finer, the portion where the actual waveform is most linear is typically between 30% and 70% points. Thus,most of the newer generation timing libraries specify slew measurement points as 30% and 70% of Vdd. However, because the transition times were previously measured between 10% and 90%, the transition times measured between 30% and 70% are usually doubled for populating the library. This is specified by the slew derate factor which is typically specified as 0.5. The slew thresholds of 30% and 70% with slew derate as 0.5 results in equivalent measurement points of 10% and 90%.

Notice that some of the hold values in the example above are negative. This is acceptable and normally happens when the path from the pin of the flipflop to the internal latch point for the data is longer than the corresponding path for the clock. Thus, a negative hold check implies that the data pin of the flip-flop can change ahead of the clock pin and still meet the hold time check.

The setup values of a flip-flop can also be negative. This means that at the pins of the flip-flop, the data can change after the clock pin and still meet the setup time check.

Can both setup and hold be negative? No; for the setup and hold checks to be consistent, the sum of setup and hold values should be positive. Thus, if the setup (or hold) check contains negative values - the corresponding hold (or setup) should be sufficiently positive so that the setup plus hold value is a positive quantity.

For flip-flops, it is helpful to have a negative hold time on scan data input pins. This gives flexibility in terms of clock skew and can eliminate the need for almost all buffer insertion for fixing hold violations in scan mode (scan mode is the one in which flip-flops are tied serially forming a scan chain - output of flip-flop is typically connected to the scan data input pin of the next flip-flop in series; these connections are for testability).

The timing models, such as NLDM, represent the delay through the timing arcs based upon output load capacitance and input transition time. In reality, the load seen by the cell output is comprised of capacitance as well as interconnect resistance. The interconnect resistance becomes an issue since the NLDM approach assumes that the output loading is purely capacitive. Even with non-zero interconnect resistance, these NLDM models have been utilized when the effect of interconnect resistance is small.

As the feature size shrinks, the effect of interconnect resistance can result in large inaccuracy as the waveforms become highly non-linear. Various modeling approaches provide additional accuracy for the cell output drivers. Broadly, these approaches obtain higher accuracy by modeling the output stage of driver by an equivalent current source.

For example, the CCS timing models provide the additional accuracy for modeling cell output drivers by using a time-varying and voltage-dependent current source. The timing information is provided by specifying detailed models for the receiver pin capacitance1 and output charging currents under different scenarios.

##CCS Receiver Pin Capacitance The receiver pin capacitance corresponds to the input pin capacitance specified for the NLDM models. Unlike the pin capacitance for the NLDM models, CCS models allow separate specification of receiver capacitance in different portions of the transitioning waveform. Due to interconnect RC and the equivalent input non-linear capacitance due to the Miller effect from the input devices within the cell, the receiver capacitance value varies at different points on the transitioning waveform.

This capacitance is thus modeled differently in the initial (or leading) portion of waveform versus the trailing portion of the waveform.

The receiver pin capacitance can be specified at the pin level (like in NLDM models) where all timing arcs through that pin use that capacitance value. Alternately, the receiver capacitance can be specified at the timing arc level in which case different capacitance models can be specified for different timing arcs. These two methods of specifying the receiver pin capacitance are described next.

Capacitance type Edge Transition Receiver_capacitance1_rise Rising Leading portion of transition Receiver_capacitance1_fall Falling Leading portion of transition Receiver_capacitance2_rise Rising Trailing portion of transition Receiver_capacitance2_fall Falling Trailing portion of transition

In the CCS model, the non-linear timing is represented in terms of output current. The output current information is specified as a lookup table that is dependent on input transition time and output load.