Hello, This is your eternal learning blog coming back to bloging the VLSI - Physical design concepts after a long haitus. In todays article, we will go back to the basics of understanding static timing analysis in nm designs. Below notes are based on this book.

Introduction:

In a chip, transistors do the computation. Metal interconnects (wires) connect those transistors together so signals can travel. As technology scales down, transistors become smaller and faster. But the wires do not scale as nicely. So, the wires start becoming a performance bottleneck.

Why interconnects affect performance:

1. Resistance increases:
   • Thinner wires -> higher resistance
   • signals take longer to travel.
2. Capacitance stays significant:
   • Wires are closer together -> more coupling capacitance.
   • More delay + signal interference (crosstalk)
3. RC delay dominates:
   • Delay =~ Resistance x capacitance
   • This wire delay can exceed transistor delay in modern nodes.

In nanometer process technologies, the coupling in the interconnect induces noise and crosstalk - either of which can limit the operating speed of a design.

A) What is static timing Analysis ? The STA is static since the analysis of the design is carried out statically and does not depend upon the data values being applied at the input pins. Given a design along with a set of inputclock definitions and the definition of the external environment of the design, the purpose of static timing analysis is to validate if the design can operate at the rated speed. That is, the design can operate safely at the specified frequency of the clocks with out any timing violations.

Some examples of timing checks are setup and hold checks. A setup check ensures that the data can arrive at a flip-flop within the given clock period. A hold check ensures that the data is held for at least a minimum time so that there is no unexpected pass-through of data through a flip-flop: that is, it ensures that a flip-flop captures the intended data correctly.

Timing Simulation Vs Timing Analysis: Static timing analysis is a complete and exhaustive verification of all timing checks of a design. Other timing analysis methods such as simulation can only verify the portions of the design that get exercised by stimulus. Verification through timing simulation is only as exhaustive as the test vectors used. To simulate and verify all timing conditions of a design with 10-100 million gates is very slow and the timing cannot be verified completely. Thus, it is very difficult to do exhaustive verification through simulation. Also simulation can not handle the effects of cross-talk, noise and on-chip variations.

Importance of interconnect delays for performance:

1. Logic cells are connected by interconnect metal traces. The parasitic RC of the metal traces impact the signal path delay through these traces. In nm designs, the parasitics of the interconnect can account for the majority of the delay and power dissipation in the design. Thus, any analysis of the design should evaluate the impact of the interconnect on the performance metrics speed, power etc. Coupling between signal traces contributes to noise, and the design verification must include the impact of the noise on the performance.
2. At the logical design phase, ideal interconnect may be assumed since there is no physical information related to the placement; there may be more interest in viewing the logic that contributes to the worst paths. Another techinique used at this tage is to estimate the length of the interconnect using a wireload model. The wireload model provides estimated RC based on the fanouts of a cell.
3. Before the routing of traces are finalized, the implementation tools use an estimate of the routing distance to obtain RC parasitics for the route. Since the routing is not finalized, this phase is called the global route phase to distinguish it from the final route phase. Affect of coupling can be analyzed only after final detailed routing is complete. An extraction tool is used to extract the detailed parasitics (RC values) from a routed design.

Summary , the statis timing analysis can be performed on a gate-level netlist depending on:

1. how interconnect is modeled - ideal interconnect, wireload model, global routes with approximate RCs or real routes with accurate RCs.
2. how clocks are modeled - whether clocks are ideal or propagated.
3. whether the coupling between signals is included - whether any crosstalk noise is analyzed.

Limitations of STA: While the timing and noise analysis do an excellent job of analyzing a design for timing issues under all possible situations, the state of the art still does not allow STA to replace simulation completely. Some of the limitations are:

1. Reset Sequence: To check if all flip-flops are reset into their required logical values after an async or sync reset.
2. X-handling: STA can do 0/1 rise/fall but can not check how unkown X is propagated in design.
3. PLL settings: Configuration may not be loaded or set properly.
4. Async clock domain crossing: STA does not check if the correct clock sync are being used. Other tools are needed to ensure that the correct clock sync are present wherever there are async clock domain crossings. Like: CDC ?
5. IO interface timing:
6. Interfaces btw analog and digital blocks: sta can not deal with analog blocks.
7. false paths: and etc.

To look at how interconnect affects reliability: like wide, more current EMIR etc To be read and updated from S Async designs and skew checks To be read and updated from S